Mirrors
/
Zelda64Recomp
mirror of https://github.com/Mr-Wiseguy/Zelda64Recomp.git
0
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add casts to mem macros

This commit is contained in:
angie 2024-05-14 10:40:15 -04:00
parent abbf090153
commit d450aa98fc
1 changed files with 14 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
include/recomp.h
View File

@ -26,33 +26,33 @@ typedef uint64_t gpr;
((gpr)(int32_t)((a) - (b))) ((gpr)(int32_t)((a) - (b)))
#define MEM_W(offset, reg) \ #define MEM_W(offset, reg) \
(*(int32_t*)(rdram + ((((reg) + (offset))) - 0xFFFFFFFF80000000))) (*(int32_t*)(rdram + ((((gpr)(reg) + (gpr)(offset))) - 0xFFFFFFFF80000000ULL)))
//(*(int32_t*)(rdram + ((((reg) + (offset))) & 0x3FFFFFF))) //(*(int32_t*)(rdram + ((((gpr)(reg) + (gpr)(offset))) & 0x3FFFFFF)))
#define MEM_H(offset, reg) \ #define MEM_H(offset, reg) \
(*(int16_t*)(rdram + ((((reg) + (offset)) ^ 2) - 0xFFFFFFFF80000000))) (*(int16_t*)(rdram + ((((gpr)(reg) + (gpr)(offset)) ^ 2) - 0xFFFFFFFF80000000ULL)))
//(*(int16_t*)(rdram + ((((reg) + (offset)) ^ 2) & 0x3FFFFFF))) //(*(int16_t*)(rdram + ((((gpr)(reg) + (gpr)(offset)) ^ 2) & 0x3FFFFFF)))
#define MEM_B(offset, reg) \ #define MEM_B(offset, reg) \
(*(int8_t*)(rdram + ((((reg) + (offset)) ^ 3) - 0xFFFFFFFF80000000))) (*(int8_t*)(rdram + ((((gpr)(reg) + (gpr)(offset)) ^ 3) - 0xFFFFFFFF80000000ULL)))
//(*(int8_t*)(rdram + ((((reg) + (offset)) ^ 3) & 0x3FFFFFF))) //(*(int8_t*)(rdram + ((((gpr)(reg) + (gpr)(offset)) ^ 3) & 0x3FFFFFF)))
#define MEM_HU(offset, reg) \ #define MEM_HU(offset, reg) \
(*(uint16_t*)(rdram + ((((reg) + (offset)) ^ 2) - 0xFFFFFFFF80000000))) (*(uint16_t*)(rdram + ((((gpr)(reg) + (gpr)(offset)) ^ 2) - 0xFFFFFFFF80000000ULL)))
//(*(uint16_t*)(rdram + ((((reg) + (offset)) ^ 2) & 0x3FFFFFF))) //(*(uint16_t*)(rdram + ((((gpr)(reg) + (gpr)(offset)) ^ 2) & 0x3FFFFFF)))
#define MEM_BU(offset, reg) \ #define MEM_BU(offset, reg) \
(*(uint8_t*)(rdram + ((((reg) + (offset)) ^ 3) - 0xFFFFFFFF80000000))) (*(uint8_t*)(rdram + ((((gpr)(reg) + (gpr)(offset)) ^ 3) - 0xFFFFFFFF80000000ULL)))
//(*(uint8_t*)(rdram + ((((reg) + (offset)) ^ 3) & 0x3FFFFFF))) //(*(uint8_t*)(rdram + ((((gpr)(reg) + (gpr)(offset)) ^ 3) & 0x3FFFFFF)))
#define SD(val, offset, reg) { \ #define SD(val, offset, reg) { \
*(uint32_t*)(rdram + ((((reg) + (offset) + 4)) - 0xFFFFFFFF80000000)) = (uint32_t)((gpr)(val) >> 0); \ *(uint32_t*)(rdram + ((((gpr)(reg) + (gpr)(offset) + 4)) - 0xFFFFFFFF80000000ULL)) = (uint32_t)((gpr)(val) >> 0); \
*(uint32_t*)(rdram + ((((reg) + (offset) + 0)) - 0xFFFFFFFF80000000)) = (uint32_t)((gpr)(val) >> 32); \ *(uint32_t*)(rdram + ((((gpr)(reg) + (gpr)(offset) + 0)) - 0xFFFFFFFF80000000ULL)) = (uint32_t)((gpr)(val) >> 32); \
} }
//#define SD(val, offset, reg) { \ //#define SD(val, offset, reg) { \
// *(uint32_t*)(rdram + ((((reg) + (offset) + 4)) & 0x3FFFFFF)) = (uint32_t)((val) >> 32); \ // *(uint32_t*)(rdram + ((((gpr)(reg) + (gpr)(offset) + 4)) & 0x3FFFFFF)) = (uint32_t)((val) >> 32); \
// *(uint32_t*)(rdram + ((((reg) + (offset) + 0)) & 0x3FFFFFF)) = (uint32_t)((val) >> 0); \ // *(uint32_t*)(rdram + ((((gpr)(reg) + (gpr)(offset) + 0)) & 0x3FFFFFF)) = (uint32_t)((val) >> 0); \
//} //}
static inline uint64_t load_doubleword(uint8_t* rdram, gpr reg, gpr offset) { static inline uint64_t load_doubleword(uint8_t* rdram, gpr reg, gpr offset) {